1. Field of the Invention
The present invention relates to a communication system, and more particularly, to a communication system for raising channel utilization rate and a communication method of the communication system for transmitting/receiving data via a plurality of communication channels.
2. Description of the Related Art
A direct memory access (DMA) controller can be used for transmitting/receiving data quickly without interference from a central processing unit (CPU) in a communication system. The DMA controller stores data received in terms of a packet unit via communication channels in a memory or transmits data stored in a memory to communication channels in terms of a packet unit. To do so, the DMA controller accesses buffer descriptors in the memory. The buffer descriptors comprise organized information on packets to be transmitted/received by the CPU via communication channels. A buffer descriptor can store information on one packet.
A start buffer descriptor pointer in the DMA controller can be set by the CPU. The DMA controller successively accesses buffer descriptors starting with a first buffer descriptor that is pointed to by the start buffer descriptor pointer and then processes packet data.
FIG. 1 is a diagram illustrating an embodiment of a buffer descriptor constituted by the CPU. Referring to FIG. 1, a buffer descriptor can include a data pointer DP, an ownership bit O, a command bit C, a status bit S, and a next buffer descriptor pointer NBDP.
The data pointer DP indicates the address in the memory at which packet data received via communication channels will be stored or the address in the memory at which packet data to be transmitted to communication channels is recorded. The ownership bit O indicates whether or not the buffer descriptor is in a CPU mode, where the buffer descriptor can be accessed by the CPU, or in a DMA mode, where the buffer descriptor can be accessed by the DMA controller. The command bit C indicates a packet data processing command. The status bit indicates the status after transmitting/receiving packet data and the type of errors in a case where errors occur. The next buffer descriptor pointer NDBP points to the next buffer descriptor to be accessed by the DMA controller.
Hereinafter, a method for processing packet data of the DMA controller accessing the buffer descriptor shown in FIG. 1 will be described.
As described above, the start buffer descriptor pointer in the DMA controller can be set by a CPU. For the convenience of explanation, suppose that the start buffer descriptor pointer of the DMA controller points to a first buffer descriptor 10_0. The DMA controller accesses the first buffer descriptor 10_0 pointed to by the start buffer descriptor pointer, and determines whether the ownership bit O indicates that the buffer descriptor is in the CPU mode or the DMA mode.
The CPU mode is a mode in which the CPU is organizing the buffer descriptor for transmitting/receiving data. After the buffer descriptor is organized, the CPU sets the ownership bit O so that the mode of the buffer descriptor is converted into the DMA mode. The DMA controller identifies the ownership bit O of the first buffer descriptor 10_0. At this time, if the ownership bit O is set (or reset), the DMA controller transmits packet data received from communication channels to a memory address pointed to by the data pointer DP and converts the mode of the buffer descriptor into the CPU mode by resetting the ownership bit O. If the mode of the buffer descriptor is converted into the CPU mode, the CPU can store information on new packet data in a buffer descriptor.
The DMA controller identifies the next buffer descriptor pointer NBDP and accesses a buffer descriptor pointed to by the next buffer descriptor pointer NBDP. At this time, if the next buffer descriptor pointer NBDP of the first buffer descriptor 10_0 indicates an address “104h”, the DMA controller accesses a buffer descriptor 20_0 having a start address of “104h”.
If the ownership bit O of the first buffer descriptor to be accessed by the DMA controller is not set yet, in other words, if the first buffer descriptor 10_0 is in the CPU mode, the DMA controller waits until the first buffer descriptor 10_0 is organized and the CPU has set the ownership bit O to indicate the DMA mode.
FIG. 2 is a diagram illustrating another embodiment of a buffer descriptor constituted by a CPU. Compared to the buffer descriptor of FIG. 1, the buffer descriptor shown in FIG. 2 does not have a next buffer descriptor. A DMA controller for accessing the buffer descriptor of FIG. 2 has a start buffer descriptor pointer for pointing to a buffer descriptor that will be accessed first and a current buffer descriptor pointer for pointing to a buffer descriptor that is currently being accessed. The initial value of the current buffer descriptor pointer is the same as that of the start buffer descriptor pointer.
Referring to FIG. 2, in the case where the start buffer descriptor pointer of the DMA controller points to an address “100h”, the DMA controller accesses a first buffer descriptor 20_0 and identifies whether the first buffer descriptor 20_0 is in the CPU mode or the DMA mode. After completing data processing of the first buffer descriptor 20_0, the DMA controller changes the value of the current buffer descriptor pointer by adding an address corresponding to the size of a buffer descriptor to the value of the current buffer descriptor pointer. Accordingly, the value of the current buffer descriptor pointer of the DMA controller is changed from “100h” to “102h”, and then the DMA controller accesses a second buffer descriptor 20 _2.
In the case of the buffer descriptor shown in FIG. 2, since the DMA controller adds an address, whose value is the size of a buffer descriptor, to the value of the current buffer descriptor pointer, it is possible to find the address to be accessed next. After all of the buffer descriptors from the first buffer descriptor 20_0 to an n-th buffer descriptor 20_n are sequentially processed, the current buffer descriptor pointer of the DMA controller becomes the start buffer descriptor pointer, and the DMA controller accesses the first buffer descriptor 20_0 and processes packet data according to information stored in the first buffer descriptor 20_0.
As described above, each of the buffer descriptors shown in FIGS. 1 and 2 has an ownership bit O for indicating whether or not the DMA controller is accessible. If a buffer descriptor to be accessed is in the CPU mode after the DMA controller identifies the ownership bit O, the DMA controller cannot process packet data transmitted/received via communication channels and waits for the buffer descriptor to change into the DMA mode.
In a communication system that receives packet data via two or more communication channels, if an error occurs in the received packet data due to the occurrence of errors in one of the two or more communication channels, the CPU resets (or sets) the ownership bit O of the buffer descriptor to the CPU mode. Thus, the DMA controller cannot access the buffer descriptor. Therefore, it is possible to prevent packet data received through the communication channels with errors from being transmitted to the memory via the DMA controller. At this time, the DMA controller waits for the buffer descriptor to be accessible. In other words, the DMA controller waits for the buffer descriptor to be in the DMA mode. When the DMA controller is on standby, packet data transmitted/received via other communication channels cannot be processed.
In a communication system that transmits/receives packet data via two or more communication channels, if an error occurs in one of the communication channels, and thus the DMA controller is in a standby mode, the DMA controller cannot process packet data transmitted via error-free communication channels.
Therefore, a need exists for a system and method for temporarily by-passing communication channel with error.